The present invention relates to a semiconductor device. More particularly, the present invention relates to a technology effectively applicable to a semiconductor device having circuit cells arranged in a multi-stage form.
FIG. 1 of Japanese Unexamined Patent Application Publication No. 2010-67799 (Patent Document 1) discloses a circuit cell for forming a logic circuit. The circuit cell has a wire 4V for supplying a power supply potential VDD, and a wire 4G for supplying a reference potential GND, extending in parallel with each other in the transverse direction in the drawing. A plurality of n channel type MISFETs and a plurality of p channel type MISFETs are arrayed between the wires 4V and 4G. Then, the circuit cells are arranged in a multi-layer form in the longitudinal direction in the drawing. Incidentally, the width of the circuit cell in the direction orthogonal to the wires 4V and 4G is referred to as the height of the circuit cell.